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Preliminary Information
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M2050/51/52 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables.
FEATURES
Integrated SAW delay line; Output of 15 to 700 MHz * Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50Hz to 80MHz) Pin-selectable PLL divider ratios support 64b/66b and FEC encoding/decoding ratios:
* M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC * M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE * M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
28 29 30 31 32 33 34 35 36
M2050 M2051 M2052
(Top View)
18 17 16 15 14 13 12 11 10
P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
Figure 1: Pin Assignment
Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance LVPECL clock output (CML and LVDS options available) Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Lock (LOL) output pin Narrow Bandwidth control input (NBW Pin) Hitless Switching (HS) options with or without Phase Build-out (PBO) available; performance conforms with SONET (GR-253) /SDH (G.813) MTIE and TDEV during reference clock reselection Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Example I/O Clock Frequency Combinations
Using M2050 Mapper PLL Base Input Rate (MHz)1 625.0000 625.0000 644.5313 Mapper Ratio Mfec / Rfec
(Pin Selectable)
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
VCSO* and Base Output Rate (MHz)2 644.5313 669.6429 690.5692
33 / 32 15 / 14 15 / 14
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be base rate divided by "Mfin". Note 2: Output rate can be base rate divided by "P". * Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Loop Filter
M2050, 51, 52
NBW LOL
MUX
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL FEC_SEL1:0 FIN_SEL1:0 P_SEL2:0
2
Phase Detector
0 1
Rfec Div
VCSO
Mfec Div
Mfec and Rfec Divider LUT
Mfin Divider
(1, 4, 5, 25)
P Divider
Mfin Divider LUT P Divider LUT
(1, 4, 5, 25 or TriState)
TriState
FOUT0 nFOUT0 FOUT1 nFOUT1
2
3
Figure 2: Simplified Block Diagram
M2050/51/52 Datasheet Rev 1.0
M2050/51/52 SAW PLL for 10GbE 64b/66b FEC
Revised 23Jun2005 Communications Modules
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M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12 13 15 16 17 18 25 20 21 22 23 24 27 28 29 30 31 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1 nFOUT1 FOUT0 nFOUT0 P_SEL1 P_SEL0 P_SEL2 nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 FIN_SEL1 FIN_SEL0 FEC_SEL0 FEC_SEL1 LOL I/O Configuration Description
Ground Input Output Input Power Output Output Input Input Input Input Input Input No internal terminator No internal terminator
Power supply ground connections. External loop filter connections. See Figure 5, External Loop Filter, on pg. 8. Power supply connection, connect to +3.3V. Clock output pair 1. Differential LVPECL. Clock output pair 0. Differential LVPECL.
, P divider selection. LVCMOS/LVTTL. See Table 7, Internal pull-down resistor1 Post-PLL Look-Up Table (LUT), on pg. 4. P Divider Reference clock input pair 1. Differential LVPECL or LVDS. Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS. Internal pull-down resistor1 Biased to Vcc/2 2 Internal pull-down resistor 1 Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair 0. Differential LVPECL or LVDS. Resistor bias on inverting terminal supports TTL or LVCMOS. Biased to Vcc/2 2
See Internal pull-down resistor1 Input clock frequency selection. LVCMOS/LVTTL. 3. Table 3 Mfin Divider Look-Up Tables (LUT) on pg. Mfec and Rfec divider value selection. LVCMOS/ LVTTL. Internal pull-down resistor1 See Tables 4, 5,and 6 on pg. 3. Loss of Lock indicator output. Asserted when internal PLL is not tracking the input reference for frequency and phase. 3 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100k. Logic 0 - Wide bandwidth, RIN = 100k.
Table 2: Pin Descriptions
Output
32 34, 35, 36
NBW DNC
Input
Internal pull-UP resistor1 Do Not Connect.
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10. Note 2: Biased toVcc/2, with 50k to Vcc and 50k to ground. See Differential Inputs Biased to VCC/2 in DC Characteristics on pg. 10. Note 3: See LVCMOS Output in DC Characteristics on pg. 10.
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M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information
DETAILED BLOCK DIAGRAM
R LOOP C LOOP R POST C POST C POST R LOOP C LOOP OP_OUT R POST nOP_OUT nVC VC
External Loop Filter Components
M2050, 51, 52
NBW LOL
MUX Phase Detector Rfec Div
OP_IN
nOP_IN
Hitless Switch Option Phase Buildout Option
R IN
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL
0
R IN
1
Loop Filter Amplifier Mfin Divider (1, 4, 5, 25)
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
Mfec Div
FEC_SEL1:0
Mfec/Rfec Divider LUT P Divider (1, 4, 5, 25, or TriState)
FOUT0 nFOUT0 FOUT1 nFOUT1
FIN_SEL1:0
Mfin Divider LUT P Divider LUT
P_SEL2:0
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
Mfin Divider Look-Up Tables (LUT) The FIN_SEL1:0 pins select the feedback divider value ("Mfin"). Since the VCSO frequency is fixed, this allows input reference selection. The look-up tables vary by device variant.
M2050/51/52: Mfin Value LUT
FIN_SEL1:0
Mfec and Rfec Divider Look-Up Tables (LUTs) The FEC_SEL pins select the Mfec/Rfec divider ratio. The look-up tables vary by device variant. The Mfec and Rfec values also establish phase detector frequency. A lower phase detector frequency improves jitter tolerance and lowers loop bandwidth.
M2050: Map LUT (10GbE to LAN, 255/238 FEC, or 255/237 FEC)
FEC_SEL1:0 Mfec Rfec 10
Mfin Sample Input Reference Freq. (MHz) Options Value For M20501, M2051 & M20522
Description
Fvcso = Base Input Base Output Rate (MHz) Rate (MHz)
0 0 1 1
0 1 0 1
25 5 4 1
25.00 125.00 156.25 625.00
Table 3: M2050/51/52: Mfin Value LUT
For M2050 with Fvcso = 644.5313 (10GbE to 10GbE LAN rate):
0 0 1 1
0 1 0 1
33 32 33 33 15 14 15 15
10GbE to 10GbE LAN 10GbE LAN repeater
625.0000 644.5313 625.0000 669.6429
644.5313 644.5313 669.6429 669.6429
For M2050 with Fvcso = 669.6429 (10GbE to 10GbE 255/238 FEC rate): 10GbE to 10GbE 255/238 FEC 10GbE 255/238 FEC repeater
Note 1: For M2050 with Fvcso = 669.6429 Note 2: For M2051 and M2052 with Fvcso = 625.0000.
For M2050 with Fvcso = 690.5692 (10GbE LAN to 10GbE LAN 255/238 FEC): 10GbE LAN to 10GbE LAN 1 0 15 14 255/238 FEC 644.5313 690.5692
1
1
15 15
10GbE LAN 255/238 FEC repeater
690.5692
690.5692
For M2050 with Fvcso = 693.4830 (10GbE LAN to 10GbE LAN 255/237 FEC): 10GbE LAN to 10GbE LAN 0 0 85 79 255/237 FEC 644.5313 693.4830
0
1
85 85
10GbE LAN 255/237 FEC repeater
693.4830
693.4830
Table 4: M2050: Map LUT (10GbE to LAN, 255/238 FEC, or 255/237 FEC)
M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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M2051: De-map LUT (10GbE LAN or 255/238 FEC to 10GbE)
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information P Divider Look-Up Table (LUT) The P_SEL2:0 pins select the P divider values, which set the output clock frequencies. A P divider of value of 1 will provide a 625.00MHz output when using a 625.00MHz VCSO, for example. P divider values of 4, 5, or 25 are also available, plus a TriState mode. The outputs can be placed into the valid state combinations as listed in Table 7. (The outputs cannot each be placed into any of the five available states independently.)
P Value
P_SEL2:0
Use this option to demap from either "10GbE LAN" or "10GbE 255/238 FEC" encoded to "10GbE". Also use this option to operate in 10GbE repeater mode.
The de-mapper FEC PLL ratios (in Table 5) enables the M2051-11-625.0000 to accept "base" input reference frequencies of: 625.00MHz ("10GbE"), 644.5313MHz ("10GbE LAN"), and 669.6429MHz ("10GbE 255/238 FEC").
FEC_SEL1:0 Mfec Rfec 10
Description
Fvcso = Base Input Base Output Rate (MHz) Rate (MHz)
for FOUT0 for FOUT1 25 1 25 4 1 1 4 1 5 5 4 4 5 4 TriState TriState
Output Frequency (MHz)
FOUT0 FOUT1
M2050-625.0000
For M2051 with Fvcso = 625.00
0 0 1 1
0 1 0
32 32 28
33 32 30
10GbE LAN to 10GbE 10GbE jitter attenuator 10GbE 255/238 FEC to 10GbE
644.5313 625.0000 669.6429
625.0000 625.0000 625.0000
1 14 15 10GbE 255/238 FEC to 10GbE 669.6429 625.0000 Table 5: M2051: De-map LUT (10GbE LAN or 255/238 FEC to 10GbE)
The Mfec divider value for the first three settings allows one set of passive filter components to be used for all three of these modes. The fourth setting maps "10GbE 255/238 FEC" using the lowest Mfec value possible. Use this setting to produce the maximum loop bandwidth. This option de-maps from both "10GbE LAN 255/237 FEC" and "10GbE LAN 255/238 FEC" to "10GbE LAN". Also use this option to operate in 10GbE LAN repeater mode.
The de-mapper FEC PLL ratios (in Table 6) enables the M2052-11-625.0000 to accept "base" input reference frequencies of: 644.5313MHz ("10GbE LAN"), 690.5692MHz ("10GbE LAN 255/238 FEC"), and 693.4830MHz ("10GbE LAN 255/237 FEC").
FEC_SEL1:0 Mfec Rfec 10
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
25.00 25.00 625.00 156.25 125.00 156.25 125.00 N/A
625.00 156.25 625.00 625.00 125.00 156.25 156.25 N/A
Table 7: P Divider Look-Up Table (LUT)
General Guideline for Mfec and Rfec Divider Selection When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL
M2052: De-map LUT (255/237 or 255/238 FEC to 10GbE LAN)
overly sensitive, and higher phase detector frequencies make LOL less sensitive. The LOL pin should not be used during loop timing mode.
FUNCTIONAL DESCRIPTION
The M2050/51/52 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW delay line provides low jitter signal performance and establishes the output frequency of the VCSO (Voltage Controlled SAW Oscillator). In a given M2050/51/52 device, the VCSO center frequency is fixed. A common center frequency is 625.00MHz, for 10GbE 64b/66b optical network applications. The VCSO center frequency is specified at time of order (see "Ordering Information" on pg. 12). The VCSO has a guaranteed tuning range of 120 ppm (commercial temperature grade). Pin selectable dividers are used within the PLL and for the output clock. This enables tailoring of device functionality and performance. The FEC feedback and reference dividers (the "Mfec Divider" and "Rfec Divider") provide the multiplication ratios necessary to accomodate clock translation for both forward and inverse Forward Error Correction. The Mfec and Rfec
Description
Fvcso = Base Input Base Output Rate (MHz) Rate (MHz)
For M2052 with Fvcso = 625.00
0 0 1 1
0 1 0 1
79 79 84 84
85 79 90 84
10GbE LAN 255/237 FEC to 10GbE LAN 10GbE LAN jitter attenuator 10GbE LAN 255/238 FEC to 10GbE LAN 10GbE LAN jitter attenuator
693.4830 644.5313 690.5692 644.5313
625.0000 625.0000 625.0000 625.0000
Table 6: M2052: De-map LUT (255/237 or 255/238 FEC to 10GbE LAN)
Use this option for multi-rate de-mapping applications that require one set of PLL passive filter values to operate over both "10GbE LAN 255/237 FEC" and "10GbE LAN 255/238 FEC". The Mfec divider value is kept nearly constant to maintain similar loop bandwidth using one set of external filter component values.
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dividers also control the phase detector frequency. The feedback divider (labeled "Mfin Divider") provides the broader division options needed to accomodate various reference clock frequencies. For example, the M2051-11-625.0000 (see "Ordering Information" on pg. 12) has a 625.00MHz VCSO frequency:
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information Configuration of single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50k to Vcc and 50k to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure 4.
* The de-mapper FEC PLL ratios (in Tables 5 and 6)
enable the M2051-11-625.0000 to accept "base" input reference frequencies of: 625.00MHz ("10GbE"), 644.5313MHz ("10GbE LAN"), and 669.6429MHz
("10GbE 255/238 FEC").
LVCMOS/ LVTTL 50k X
VCC 50k
MUX
0
VCC 127
50k
* The Mfin feedback divider enables the actual input
1
reference clock to be the base input frequency divided by 1, 4, 5, or 25. Therefore, for the base input frequency of 625.00MHz, the actual input reference clock frequencies can be: 625.00, 156.25, 125.00, and 25.00MHz. (See Table 3 on pg. 3.)
LVPECL
82
VCC 127
50k
VCC 50k
82
50k
REF_SEL
Key to Device Variants and Look-up Table Options
Device Variant M2050 M2051 M2052 Look-up Table Option Mfin Lookup Table is: Mfec Look-up Table is: Table 4 (mapper LUT) Table 3 Table 5 (de-mapper LUT) Table 6 (de-mapper LUT)
Table 8: Key to Device Variants and Look-up Table Options
Figure 4: Input Reference Clocks
Differential Inputs
The M2050/51/52 includes a Loss of Lock (LOL) indicator, which provides status information to system management software. A Narrow Bandwidth (NBW) control pin is provided as an additional mechanism for adjusting PLL loop bandwidth without affecting the phase detector frequency. Options are available for Hitless Switching (HS) with or without Phase Build-out (PBO). Performance conforms with SONET/ SDH MTIE and TDEV during a reference clock reselection. Allowance for a single-ended input has been facilitated by a unique input resistor bias scheme, which is described next and shown in Figure 4. Input Reference Clocks Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal (such as LVPECL or LVDS) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input).
A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal.
Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 (the 127 and 82 resistors) is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the 50 load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are connected to the non-inverting reference input pin (DIF_REF0 or DIF_REF1). The inverting reference input pin (nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting input pin (nDIF_REF0 or nDEF_REF1) is left floating (not connected), the input will self-bias at VCC/2.
PLL Operation The M2050/51/52 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. The PLL will work correctly, meaning it will phase-lock the VCSO output to the input reference clock, when the internal phase detector inputs are able to run at the same frequency. This means the PLL dividers must be set appropriately and a suitable reference frequency must be chosen for the intended output frequency. When the PLL is not set up appropriately, the VCSO is
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forced to its upper or lower operating limit which is typically about 250 ppm above or below the VCSO center frequency (no more than 500 ppm above or below). In normal phase-locked condition, the instantaneous phase error is measured by the phase detector and is converted to charge pump current pulses. These current pulses are then integrated by the external loop filter to create a VCSO control voltage. The loop filter acts as a low pass filter to remove unwanted reference clock jitter above a determined frequency or PLL bandwidth. For reference phase jitter frequencies within the loop bandwidth, phase jitter amplitude is passed on to the output clock according to the PLL loop frequency response curve. The relationship between the nominal VCSO center frequency (Fvcso), the Mfin divider, the Mfec divider, the Rfec divider, and the input reference frequency (Fin) is: Mfec Fvcso = Fin x Mfin x ------------Rfec The Mfec, Rfec, and Mfin dividers can be set by pin configuration using the input pins FEC_SEL1, FEC_SEL0,
FIN_SEL1, and FIN_SEL0.
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information TriState, in which case the net goes to a high impedance and the logic value floats.) The 50 impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external 50 generator to validate the integrity of clock net and the clock load.
Any unused output (single-ended or differential) should be left unconnected (floating) in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO.
Narrow Bandwidth (NBW) Control Pin A Narrow Loop Bandwidth control pin (NBW pin) is included to enable adjustment of the PLL loop bandwidth. In wide bandwidth mode (NBW=0), the internal resistor Rin is 100k . With the NBW pin asserted (NBW=1), the internal resistor Rin is changed to 2100k . This lowers the loop bandwidth by a factor of about 21 (approximately 2100 / 100) and lowers the damping factor by a factor of about 4.6 (the square root of 21), assuming the same external loop filter component values. Loss of Lock Indicator (LOL) Output Pin Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic 0. Under circumstances when the VCSO cannot fully phase lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector) the LOL output goes to logic 1. The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current LVCMOS output.
Guidelines for Using LOL
Post-PLL Divider The M2050/51/52 also features a post-PLL (P) divider. Through use of the P divider, the device's output frequency (Fout) can be that of the VCSO (such as 625.00MHz) or the VCSO frequency divided by 4, 5 or
25.
The P_SEL2:0 pins select the value for the P divider. (See Table 7 on pg. 4.) Accounting for the P divider, the complete relationship between the input clock reference frequency (Fin) and output clock frequency (Fout) is defined as: Mfin x Mfec Fvcso Fout = ------------------- = Fin x -------------------------------P Rfec x P
Due to the narrow tuning range of the VCSO (+200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. TriState The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. A logic 0 is then present on the clock net. The impedance of the clock net is then set to 50 by the external circuit resistors. (This is in distinction to a CMOS output in
M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
In a given application, the magnitude of peak-to-peak jitter at the phase detector will usually increase as the Rfec divider is increased. If the LOL pin will be used to detect an unusual clock condition, or a clock fault, the FEC_SEL1:0 pins should be set to provide a phase detector frequency of 5MHz or greater (the phase detector frequency is equal to Fin divided by the Rfec divider). Otherwise, false LOL indications may result. A phase detector frequency of 10MHz or greater is desirable when reference jitter is over 500ps, or when the device is used within a noisy system environment. LOL should not be used when the device is used in a loop timing application.
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Optional Hitless Switching and Phase Build-out The M2050/51/52 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to "Ordering Information" on pg. 12. The Hitless Switching feature (with or without Phase Build-out) is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. The Hitless Switching sequence is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR (Clock & Data Recovery unit) in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs (digital PLL), especially those that do not include a post de-jitter APLL (analog PLL). When the M2050/51/52 is operating in wide bandwidth mode (NBW=0), the optional Hitless Switching function puts the device into narrow bandwidth mode when activated. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock phase change complies with MTIE and TDEV specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock changes. The optional proprietary Phase Build-out (PBO) function enables the PLL to absorb most of the phase change of the input clock during reference switching. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See "Guidelines for Using LOL" on pg. 6 for information regarding the phase detector frequency.
HS/PBO Sequence Trigger Mechanism
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information
HS/PBO Operation
Once triggered, the following HS/PBO sequence occurs: 1. The HS function disables the PLL Phase Detector and puts the device into NBW (narrow bandwidth) mode. The internal resistor Rin is changed to 2100k . See the Narrow Bandwidth (NBW) Control Pin on pg. 6. 2. If included, the PBO function adds to (builds out) the phase in the clock feedback path (in VCSO clock cycle increments) to align the feedback clock with the (new) reference clock input phase. 3. The PLL Phase Detector is enabled, allowing the PLL to re-lock. 4. Once the PLL Phase Detector feedback and input clocks are locked to within 2 nsec for 8 consecutive cycles, a timer (WBW timer) for resuming wide bandwidth (in 175 nsec) is started. 5. When the WBW timer times out, the device reverts to wide loop bandwidth mode (i.e., Rin is returned to 100k) and the HS/PBO function is re-armed. The LOL pin will indicate lock status on a cycle-to-cycle basis and may be intermittent until PLL phase lock has fully stabilized.
The HS function (or the combined HS/PBO function) is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M2050/51/52, or a M2050/51/52 clock reference mux reselection.
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External Loop Filter To provide stable PLL operation, the M2050/51/52 requires the use of an external loop filter. This is provided via the provided filter pins (see Figure 5). Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information PLL bandwidth is affected by the "Mfec" value and the "Mfin" value, as well as the VCSO frequency. The FEC_SEL setting can be used to actively change PLL loop bandwidth in a given application. See "Mfec and Rfec Divider Look-Up Tables (LUTs)" on pg. 3. See Tables 9, 10, and 11, Example External Loop Filter Component Values, on pg. 8. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
VC
6 7
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
nOP_IN
Figure 5: External Loop Filter
Refer to the M2050/51/52 product web page at www.icst.com/products/summary/m2050-2052.htm for additional product information.
Example External Loop Filter Component Values for M2050-11-644.5313 and M2050-11-669.6429
VCSO Parameters: KVCO = 800kHz/V, RIN = 100k (pin NBW = 0), VCSO Bandwidth = 700kHz. F Ref (MHz) Device Configuration F VCSO FIN_ FEC_ Mfin M R ... SEL1:0 (MHz) Phase Det. Freq. (MHz) Example Loop Filter Component Values Nominal Performance With Values R Loop C Loop R Post C Post PLL Loop Damping Passband Post Filter Bandwidth Factor Peaking (dB) Bandwidth
125.00 125.00
644.5313 0 1 0 0 5 669.6429 0 1 1 0 5
33 32 15 14
3.9063 8.9286
61.9k 44.2k
1.0F 59.0k 1000pF 1.0F 38.3k 1000pF
577Hz 908Hz
6.8 7.2
0.043 0.039
2.7kHz 4.1kHz
Table 9: Example External Loop Filter Component Values for M2050-11-644.5313 and M2050-11-669.6429
Example External Loop Filter Component Values for M2051-11-625.0000
VCSO Parameters: KVCO = 800kHz/V, RIN = 100k (pin NBW = 0), VCSO Bandwidth = 700kHz. F Ref (MHz) Device Configuration F VCSO FIN_ FEC_ Mfin M R ...SEL1:0 (MHz) Phase Det. Freq. (MHz) Example Loop Filter Component Values Nominal Performance With Values R Loop C Loop R Post C Post PLL Loop Damping Passband Post Filter Bandwidth Factor Peaking (dB) Bandwidth
644.5313 625.0000 1 1 0 0
32 33 19.5313
28.0k
1.0F 15.0k 1000pF 1.25kHz
7.0
0.04
10.6kHz
Example External Loop Filter Component Values1 for M2052-11-644.5313
Device Configuration F VCSO FIN_ FEC_ Mfin M R ...SEL1:0 (MHz)
Table 10: Example External Loop Filter Component Values for M2051-11-625.0000
VCSO Parameters: KVCO = 800kHz/V, RIN = 100k (pin NBW = 0), VCSO Bandwidth = 700kHz. F Ref (MHz) Phase Det. Freq. (MHz) Example Loop Filter Component Values Nominal Performance With Values R Loop C Loop R Post C Post PLL Loop Damping Passband Post Filter Bandwidth Factor Peaking (dB) Bandwidth
693.4830 644.5313 1 1 0 0 1
79 85
8.1586
51.0k
1.0F 33.2k 1000pF
986Hz
8.1
0.031
4.8kHz
Table 11: Example External Loop Filter Component Values for M2052-11-644.5313
Note 1: KVCO , VCSO Bandwidth, Mfin x Mfec Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com.
M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
8 of 12 Communications Modules
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Integrated Circuit Systems, Inc.
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
o
-45 to +100
C
Table 12: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature Commercial Industrial
V
oC oC
0 -40
+70 +85
Table 13: Recommended Conditions of Operation
M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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Integrated Circuit Systems, Inc.
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135 0.15 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 0.5
Typ 3.3 175
Max 3.465 225
Unit Conditions
Power Supply VCC ICC All Differential Inputs Differential Inputs with Pull-down Differential Inputs Biased to VCC/2 1 All LVCMOS / LVTTL Inputs LVCMOS / LVTTL Inputs with Pull-down LVCMOS / LVTTL Inputs with Pull-UP Differential Outputs VP-P VCMR CIN IIH IIL IIH IIL Rbias VIH VIL CIN IIH IIL IIH IIL Rpullup VOH VOL VP-P LVCMOS Output VOH VOL
Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage Common Mode Input Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Biased) 1 Input Low Current (Biased) Biased to Vcc/2 1 Input High Voltage Input Low Voltage Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Pull-UP) Input Low Current (Pull-UP) Internal Pull-UP Resistance Output High Voltage Output Low Voltage Peak to Peak Output Voltage Output High Voltage Output Low Voltage
2
1
V mA V
Vcc - .85 V 4 150
pF A A k
VCC = VIN = 3.456V
DIF_REF0, DIF_REF1
-5
50 150
Rpulldown Internal Pull-down Resistance
nDIF_REF0, nDIF_REF1
A A k
-150
(Note 1) 2
VIN = 0 to 3.456V
REF_SEL, FIN_SEL1, FIN_SEL0, FEC_SEL1, FEC_SEL0, P_SEL2, P_SEL1, P_SEL0, NBW REF_SEL, FIN_SEL1, FIN_SEL0, FEC_SEL1, FEC_SEL0, P_SEL2, P_SEL1, P_SEL0
Vcc + 0.3 V 0.8 4 150
-0.3
V pF A A k
VCC = VIN = 3.456V
-5
50 5
Rpulldown Internal Pull-down Resistance
A A k
NBW
-150
50 Vcc - 1.4 Vcc - 2.0 0.4 2.4 GND
VCC = 3.456V VIN = 0 V
FOUT0, nFOUT0, FOUT1, nFOUT1
Vcc - 1.0 V Vcc - 1.7 V 0.85
V V V IOH= 1mA IOL= 1mA
LOL
VCC
0.4
Note 1: Biased to Vcc/2, with 50k to Vcc and 50k to ground. See Figure 4, Input Reference Clocks, on pg. 5 Note 2: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 11.
Table 14: DC Characteristics
M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
10 of 12 Communications Modules
Revised 23Jun2005 w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminary Information
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT0, nFOUT0, FOUT1, nFOUT1 Commercial Industrial 10 15
Typ
Max 700 700
Unit Conditions
FIN FOUT APR KVCO PLL Loop Constants 1 RIN
Input Frequency Output Frequency VCSO Absolute Pull-Range VCO Gain Internal Loop Resistor
MHz MHz ppm ppm kHz/V k k kHz dBc/Hz
Fin=25.00 MHz Mfec=Rfec
120 50
200 150
800 100 2100 700
Wide Bandwidth Narrow Bandwidth
BWVCSO VCSO Bandwidth n Phase Noise and Jitter J(t) odc tR tF Single Side Band Phase Noise @625.00MHz Jitter (rms) @625.00MHz Output Duty Cycle 2
FOUT0, nFOUT0, FOUT1, nFOUT1 1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz
P = 5 or 25 P = 1 or 4 2
-72 -94 -123
0.25 0.25 35 40 200 40 50 450 450 0.5 0.5 65 60 500 500
dBc/Hz Mfin=25, dBc/Hz ps ps % % ps ps
20% to 80% 20% to 80%
Output Rise Time Output Fall Time
2
FOUT0, nFOUT0, FOUT1, nFOUT1
200
Table 15: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Tables 9, 10, and 11, Example External Loop Filter Component Values, on pg. 8. Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time Output Duty Cycle
nFOUT FOUT 20% tF VP-P tPW (Output Pulse Width) tPW tPERIOD
80% Clock Output 20% tR
80%
odc =
tPERIOD
Figure 6: Output Rise and Fall Time
Figure 7: Output Duty Cycle
M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
11 of 12 Communications Modules
Revised 23Jun2005 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
Preliminary Information
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 8: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme Part Number:
Divider Look-up Table Option See Table 8, page 5.
Standard VCSO Output Frequencies (MHz)* 622.0800 669.3120 669.3266 669.6429 670.8386 672.1600 690.5692 625.0000 627.3296 644.5313 666.5143 669.1281
M205x- yz - xxx.xxxx
Output type 1 = LVPECL (For CML or LVDS clock output, consult factory) Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) PLL Frequency (MHz) See Table 16, right. Consult ICS for other frequencies.
Table 16: Standard VCSO Output Frequencies
Figure 9: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1, 4, 5, or 25.
Consult ICS for the availability of other PLL frequencies.
Example Part Numbers
VCSO Frequency (MHz) Temperature 625.0000 644.5313
commercial industrial commercial industrial
Order Part Number (Examples) M2051 - 11 - 625.0000 or M2052- 11 - 625.0000 M2051 - 11I 625.0000 or M2052- 11I 625.0000 M2050 - 11 - 644.5313 M2050 - 11I 644.5313
Table 17: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2050/51/52 Datasheet Rev 1.0 Integrated Circuit Systems, Inc.
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